This application is related to the following co-pending U.S. patent application, filed on even date herewith: xe2x80x9cIntegrated Circuit Package Substrate with High Density Routing Mechanismxe2x80x9d by Mora et al.
1. Field of Invention
This invention relates to integrated circuit packaging, and more particularly, to a packaging layout that provides high density routing of signal lines as differential pairs with approximately equal trace lengths and as a pair of signal conductor planes embedded between power and ground planes and multiple voltage supplies within the package substrate.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate, which are to be connected to external devices, may be formed such that these lines terminate at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit may typically be secured within a protective semiconductor device package. Each I/O pad of the integrated circuit may be connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires may be used to connect the I/O pads of the chip to terminals of the device package. Some types of device packages have terminals called xe2x80x9cpinsxe2x80x9d for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called xe2x80x9cleadsxe2x80x9d for attachment to flat metal contact regions on an exposed surface of a PCB.
The I/O pads of the integrated circuit may be coupled to terminals of the device package configured to supply power from one voltage supply power plane to input/output drivers of the I/O. Integrated circuits are increasingly being designed to include input/output drivers requiring different voltage supplies on the same die. The location and number of input/output drivers requiring different voltage supplies may also vary in location and number depending upon the integrated circuit design. Therefore, each different integrated circuit design may require a custom designed package substrate. For example, each substrate would have to be laid out and designed thereby requiring engineering resources, increasing costs due to the separate tooling costs associated with each different substrate, and increasing the complexity of controlling the inventory of multiple different substrates. Therefore, current substrate design methodologies can not accommodate the different voltage supplies required by input/output drivers at acceptable costs.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more circuits onto single silicon substrates. As the number of circuits on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well as the complexities and costs of the device packages. Constraints of high volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. For example, mishandling may result in a loss of lead coplanarity, thereby adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Unlike more conventional peripheral-terminal device packages, grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal traces from the chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. A BGA device package includes a chip mounted upon a larger substrate substantially made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina (Al2O3), or aluminum nitride (AIN)). Many BGA device packages have die areas dimensioned to receive integrated circuit chips and use established wire bonding techniques to electrically connect the I/O pads of the chips to corresponding flat metal xe2x80x9csignal bonding padsxe2x80x9d adjacent to the die areas. During wire bonding, the I/O pads of the chip may be electrically connected to corresponding signal bonding pads by fine metal wires (i.e., bonding wires). The substrate may include one or more layers of signal lines (i.e., signal traces or interconnects) which may connect signal bonding pads to corresponding members of a set of ball pads arranged in a two-dimensional array across the underside surface of the device package. Solder balls may be attached to the ball pads, and function as device package terminals. The resulting solder balls on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. During PCB assembly, the solder balls are placed in physical contact with corresponding ball pads of the PCB. The solder balls are then heated long enough for the solder to flow. When the solder cools, the ball pads on the underside of the package are electrically and mechanically coupled to ball pads of the PCB.
A BGA device package on a plastic carrier is known as a plastic ball grid array (PBGA) device. A PBGA, may include, for example, four conductive layers separated by three dielectric layers. The top conductive layer includes signal traces, the second conductive layer is a ground plane, the third conductive layer includes signal traces, and the bottom conductive layer is a power plane. A die is bonded to the top of this package. The die may be wirebonded to the substrate, which may be molded to cover and protect the die and the gold wire.
As dies become more dense and complex, the signal trace density of packages also increases. There are at least two problems associated with increases in signal trace density. First, the area on the signal trace layer may be insufficient for the required signal traces. Second, increasing signal trace density on a package may lead to increased cross talk between the signal traces and overall noise of the package. Therefore, current wire bonding layer methodologies may not accommodate the number of signal traces without violating current assembly or substrate design rules.
The problems outlined above may be in large part addressed by a package that includes a substrate having multiple signal voltage power supplies and/or high density signal routing. In an embodiment, a semiconductor substrate may include signal bonding pads formed upon an upper surface of the substrate. The substrate may also include balls formed upon a lower surface of the substrate. The substrate may further include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface of the substrate. In addition, the substrate may include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. In an embodiment, the voltage supply plane may include at least four segmented planes. In another embodiment, the voltage supply plane may include 16 segmented planes. In a further embodiment, a number of the segmented voltage supply connections may equal a number of the segmented planes.
Vias may electrically connect the segmented voltage supply connections to the segmented planes. The substrate may also include signal traces extending from the signal bonding pads to the balls. The signal traces may extend from the signal bonding pads such that the signal traces can be coupled to input/outputs of an integrated circuit. The vias may provide a reference for a substantial portion of a length of the signal traces. In addition, the signal traces may be referenced to the segmented planes. The segmented planes may have supply voltages corresponding to supply voltages required by input/output drivers of the input/outputs to which the signal traces are connected.
In an embodiment, at least two of the segmented planes may have different voltage supplies. For example, each of the segmented voltage supply connections is configurable to supply power to a portion of input/output drivers of an integrated circuit. Voltage supplies of the segmented planes may be determined based on voltage requirements of the portions of the input/output drivers. In addition, input/output drivers of an integrated circuit requiring different voltage supplies may be electrically connected to different segmented voltage supply connections.
In another embodiment, the substrate may include a core voltage power ring separated into quadrants spaced across the upper surface. Two of the quadrants may be connected to a first voltage plane, and the other two quadrants may be connected to a second voltage plane. The first voltage plane may have a supply voltage different than the second voltage plane.
An additional embodiment relates to a semiconductor substrate that includes a signal voltage power ring formed on an upper surface of the substrate and spaced from an area adapted to receive an integrated circuit. The signal voltage power ring may be separated into segmented voltage supply connections laterally spaced across the upper surface. The substrate may also include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. In addition, vias may electrically connect the segmented voltage supply connections to the segmented planes. In an embodiment, the substrate may include a ground ring formed on the upper surface and spaced closer to the area than the signal voltage power ring. In addition, the substrate may include a core voltage power ring formed on the upper surface and spaced closer to the area than the signal voltage power ring. In an alternative embodiment, the positions of the signal voltage power ring and the ground ring may be switched with the core voltage power ring spaced between these rings.
In an embodiment, the substrate may further include a first row of signal bonding pads spaced across the upper surface along a first line and spaced farther from the area than the signal voltage power ring. The substrate may also include a second row of signal bonding pads spaced across the upper surface along a second line that may or may not be parallel to the first line and spaced father from the area than the signal voltage power ring. The first row of signal bonding pads may be spaced farther from the area than the second row of signal bonding pads. In an additional embodiment, the substrate may include signal traces electrically connected to the first row and signal traces electrically connected to the second row of signal bonding pads. The signal traces electrically connected to the first row of signal bonding pads may be routed on a first layer of the substrate, and the signal traces electrically connected to the second row of signal bonding pads may be routed on a second layer of the substrate.
In an embodiment, the signal traces may be routed as differential pairs with approximately equal trace lengths. In an additional embodiment, the signal traces electrically connected to the first row of signal bonding pads may be dielectrically spaced between a first voltage plane and a first ground plane. In one such embodiment, the signal traces electrically connected to the second row of signal bonding pads may be dielectrically spaced between a second voltage plane and a second ground plane. In an alternative embodiment, the signal traces electrically connected to the first row of signal bonding pads may be formed across the upper surface. In a further embodiment, vias electrically coupled to the second row of signal bonding pads may be arranged in adjacent pairs with gaps between the adjacent pairs.
An additional embodiment relates to an integrated circuit package that includes an integrated circuit placed upon an upper surface of a semiconductor substrate. The package may also include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface. The integrated circuit may include first and second input/output,drivers. The first input/output driver may be electrically connected to a first segmented voltage supply connection, and the second input/output driver may be electrically connected to a second segmented voltage supply connection. The input/output drivers may be electrically connected to the segmented voltage supply connections by wires. In addition, the package may include a voltage supply plane separated into segmented planes formed within the substrate. In an embodiment, a first segmented plane may be adapted to supply a first voltage to the first segmented voltage supply connection. In addition, a second segmented plane may be adapted to supply a second voltage to the second segmented voltage supply connection. The first voltage may be different than the second voltage.
Another embodiment relates to a semiconductor substrate that includes signal bonding pads formed upon an upper surface of the substrate arranged in a first row and a second row. The first row may or may not be parallel to the second row. In an embodiment, an area on the upper surface may be adapted to receive an integrated circuit. In such an embodiment, the first row of signal bonding pads may be spaced farther from the area than the second row of signal bonding pads. The substrate may also include first signal traces electrically connected to the first row of signal bonding pads. The first signal traces may be routed on a first layer of the substrate. In addition, the substrate may include second signal traces electrically connected to the second row of signal bonding pads. The second signal traces may be routed on a second layer of the substrate. The first layer may be formed across the upper surface, and the second layer may be dielectrically spaced between a voltage plane and a ground plane. The substrate may further include balls formed on a lower surface of the substrate.
In an embodiment, the first and second signal traces may be routed as differential pairs with approximately equal trace lengths. In another embodiment, all of the first and second signal traces may be routed as differential pairs. In a further embodiment, the second signal traces may include vias arranged in adjacent pairs with gaps between the adjacent pairs. The gaps may provide continuity for a ground plane to which the second signal traces are referenced.
In an additional embodiment, the substrate may include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface. Such a substrate may also include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. Vias may electrically connect the segmented voltage supply connections to the segmented planes. In a further embodiment, the substrate may include a core voltage power ring separated into quadrants spaced across the upper surface. Two of the quadrants may be connected to a first voltage plane, and the other two quadrants may be connected to a second voltage plane.
An additional embodiment relates to a semiconductor substrate that includes signal bonding pads formed upon an upper surface of the substrate arranged in a first row and a second row. The first row may or may not be parallel to the second row. The substrate may also include first signal traces electrically connected to the first row of signal bonding pads. The first signal traces may be routed on a first layer of the substrate dielectrically spaced between a first voltage plane and a first ground plane. In an embodiment, the first layer may be spaced symmetrically between the first voltage plane and the first ground plane. In one embodiment, all of the signal traces on the first layer may be routed as differential pairs. In an additional embodiment, the first signal traces may include blind vias extending from the upper surface to the first layer and blind vias extending from the first layer to a lower surface of the substrate.
In addition, the substrate may include second signal traces electrically connected to the second row of signal bonding pads. The second signal traces may be routed on a second layer of the substrate dielectrically spaced between a second voltage plane and a second ground plane. In an embodiment, the second layer may be spaced symmetrically between the second voltage plane and the second ground plane. In another embodiment, all of the signal traces on the second layer may be routed as differential pairs. In a further embodiment, the second signal traces may include through hole vias extending from the upper surface to the second layer and blind vias extending from the second layer to a lower surface of the substrate.
A further embodiment relates to an integrated circuit package that includes an integrated circuit placed upon an area of an upper surface of a semiconductor substrate. The package may also include signal bonding pads formed upon an upper surface of the substrate arranged in a first row and a second row. The first row may or may not be parallel to the second row. In addition, the first row of signal bonding pads may be spaced farther from the area than the second row of signal bonding pads. The signal bonding pads may be electrically connected to bonding pads of the integrated circuit by wires. The package may further include signal traces electrically connected to the first row and the second row of signal bonding pads. The signal traces may be routed in differential pairs on different layers of the substrate.
In an embodiment, the package may include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface and a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. In addition, vias may electrically connect the segmented voltage supply connections to the segmented planes.